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A UART Receiver follows a UART Transmitter. It receives the serialized data and converts it back to a parallel form. The working of the receiver is a bit more complicated than the transmitter. Since UART is an Asynchronous Protocol, no clock is transmitted along the data. Therefore, the receiver has to identify the start of the incoming data frame to properly convert it to parallel form. To do this the transmitter and the receiver have to agree to the baud rate and the number of bits per frame. The transmitter and the receiver also have to agree with the length of the stop period (1 bit, 1.5 bit or 2 bits). In the given project the UART Receiver is configured for the baud rate of 1 Mbit/s, 1 stop bit, no parity or flow control. The receiver looks for the Rx_pin to go low which indicates the start bit. As the Rx_pin goes low, a Flip_Flop is Set which enables a counter which starts counting as the Rx_pin goes low. When the Counter reaches 25 (The counter is clocked at 50 Mhz in the give...

UART stands for Universal Asynchronous Receive Transmit. It is one of the most popular Asynchronous Serial Communication protocols. It is not only simple to implement but also economical to use. It uses only two wires to communicate between two devices. UART can also be implemented in a multi-drop configuration but then proper termination is necessary (see  RS-485 Wikipedia Link ). UART is capable of approximately 2-MBit/s in single-ended configuration but upto 10-Mbit/s in Differential Configuration. Higher speeds usually come at the penalty of using shorter transmission lines (also Impedance Matching is recommended). In this project ,we shall implement a UART Transmitter in an FPGA. The FPGA which was used for testing was a Xilinx Spartan-6 XC6SLX9 FPGA. The FPGA was clocked by a 50Mhz Crystal. In the project the Verilog module implemented has an 8-bit Input and the UART-Tx Output along with a Tx_Enable Input . The UART transmitter works in this way-- A Shift Register is used t...